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s6b 07 56 65 com / 96 seg drive r & controller for stn lcd july . 2002 . ver. 2 . 5 prepared by jae ho park S6B0756 specification revision history version content date contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
65 com / 96 seg driver & controller for stn lcd S6B0756 2 0.0 .initial version dec.2000 0.1 .reference circuit examples(page 26) corrected .enter calibration mode instruction deleted .otp calibration mode changed jan.2001 0.2 .enter micro processor interface protocol (page 9) mar.2001 1.0 .eliminated x5 boost.(page 1) .added vci range (page 1) .changed block diagram for integrated booster capacitors(page 3) .added otpg / otpd pin(page 3,5) .changed reference circuit examples(page 27) .changed reset mode initial operation(page 29) .added frame frequency command(page 30,39) .changed operating current(page 54) mar.2001 1.1 .changed block diagram (page 3) .changed lcd driver supply (page 4) .changed system control (page 5) .changed voltage regulator circuits (page 24) .deleted ? in case of using external resisters, ra and rb ? (page 26) .changed reference circuit examples (page 27) .changed instruction : read status ( page 32) .added instructions concerned with otp : calibration mode en (page 40) , otp write enable( page 41 ), set ov register ( page 45 ) .added otp operation (page 64) apr.2001 2.0 .added instruction concerned with otp : otp mode on/off .added otp operation .changed v0 to vout may.2001 2.1 .pad configuration .pad center coordinates june.2001 2.2 .changed lcd driving voltage dec.2001 2.3 .fix key coordinates and adjust vss pin number feb.2002 2.4 .added display example(page 42) may.2002 2.5 .changed icon(page 42) function. july.2002
S6B0756 65 com / 96 seg driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ ............ 1 features ................................ ................................ ................................ ................................ .................... 1 pad configuration ................................ ................................ ................................ ................................ .. 3 pin description ................................ ................................ ................................ ................................ ......... 7 power supply ................................ ................................ ................................ ................................ .... 7 lcd driver supply ................................ ................................ ................................ ............................. 7 system control ................................ ................................ ................................ ................................ 8 microprocessor interface ................................ ................................ ................................ ........... 9 lcd driver outputs ................................ ................................ ................................ ......................... 11 functional description ................................ ................................ ................................ ....................... 12 microprocessor interface ................................ ................................ ................................ .......... 12 display data ram (ddram) ................................ ................................ ................................ .............. 17 lcd display circuits ................................ ................................ ................................ ........................ 20 lcd driver circuit ................................ ................................ ................................ ........................... 22 power supply circuits ................................ ................................ ................................ ................... 25 reference circuit examples ................................ ................................ ................................ ..... 30 reset circuit ................................ ................................ ................................ ................................ .... 32 instruction description ................................ ................................ ................................ ...................... 33 specifications ................................ ................................ ................................ ................................ ......... 57 absolute maximum ratings ................................ ................................ ................................ ........... 57 dc characteristics ................................ ................................ ................................ ......................... 58 ac characteristics ................................ ................................ ................................ ......................... 61 reference applications ................................ ................................ ................................ ....................... 65 microprocessor interface ................................ ................................ ................................ .......... 65 connections between S6B0756 and lcd panel ................................ ................................ .......... 67 otp calibration mode ................................ ................................ ................................ ........................... 68 sequence for setting the modified electronic volume ................................ ...................... 68 otp cell structure ................................ ................................ ................................ ........................ 69 vout calibration flow ................................ ................................ ................................ ................... 69 voltages and waveforms for otp programming ................................ ................................ ... 70

S6B0756 65 com / 96 seg driver & controller for stn lcd 1 introduction the S6B0756 is a driver & controller lsi for graphic dot-matrix liquid crystal display systems. it contains 65 common and 96 segment driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip display data ram of 65 x 96 bits. it provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no external ly operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 65 common outputs / 96 segment outputs applicable duty ratios programmable duty ratio applicable lcd bias maximum display area 1/ 17 to 1/ 65 1/4 to 1/ 9 65 96 - various partial display - partial window moving & data scrolling on-chip display data ram - capacity: 65 x 96 = 6,240 bits - bit data "1": a dot of display is illuminated . bit data "0": a dot of display is not illuminated . microprocessor interface - 8-bit parallel bi-directional interface with 6800-series or 8080-series . - spi ( serial peripheral i nterface ) available . (only write operation) on-chip low power analog circuit - on-chip oscillator circuit - voltage converter ( x2, x3, x4) - voltage regulator (temperature coefficient: -0.05%/ c or external input) - on-chip electronic contrast control function (64 steps) - voltage follower (lcd bias: 1/4 to 1/ 9 ) - on-chip bias / boosting capacitor otp(one-time programmable) method for vout calibration on-chip eprom(erasable and programmable rom) for setting the offset voltage into lcd panel. operating voltage range - supply voltage (v dd ): 1 . 8 to 3 . 3 v - voltage for dc/dc converter (vci): 2.4 to 4.5 v - lcd driving voltage (v lcd = vout - v ss ): 4.0 to 12.0 v low power consumption - tbd ( internal power supply on and display off) package type - cog (gold bumped chip ) this chip is not designed for resistance to radiation or light.
65 com / 96 seg driver & controller for stn lcd S6B0756 2 block diagram figure 1 . block diagram power supply vdd v1 vss vci v / c circuit v / r circuit v / f circuit 33 common driver circuits mpu interface (parallel & serial) instruction decoder bus holder column address circuit line addres s circuit page address circuit display data ram 65 x 96 = 6 , 24 0 bits display data control circuit display timing generator circuit common output controller circuit db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) resetb ps0 rw_wr e_rd rs cs1b coms1 com63 : com32 seg95 seg94 seg93 : : seg2 seg1 seg0 com31 : com0 coms oscillator 96 segment driver circuits 33 common driver circuits i/o buffer status register instruction register internal vss1 vss2 test4 test3 test2 test1 otpg otpd vout ps1 v2 v3 v4
S6B0756 65 com / 96 seg driver & controller for stn lcd 3 pad configuration figure 2 . s6b07 56 chip configuration table 1 . s6b07 56 pad dimensions eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 124 255 123 256 100 279 99 1 s 6b 07 56x (top view) (0,0) x eeeeeeeeeeeeeeeee - - - - - - - - - - - - - - - - - - - - - eeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee item pad no. size unit x y chip size - 8 7 8 0 2 3 0 0 um pad pitch 1 to 3 8 0 3 to 9 7 7 0 9 7 to 9 9 8 0 1 0 0 to 1 0 2 8 0 1 0 2 to 1 2 0 6 0 1 2 0 to 1 2 3 8 0 1 2 4 to 1 2 6 8 0 1 2 6 to 2 5 3 6 0 2 5 3 to 2 5 5 8 0 2 5 6 to 2 5 9 8 0 2 5 9 to 2 7 7 6 0 2 7 7 to 2 7 9 8 0 bumped pad size ( top) 1 , 2 , 9 8 , 9 9 1 2 4 , 1 2 5 , 2 5 4 , 2 5 5 6 0 1 1 0 um 3 to 9 7 5 0 1 0 0 1 0 0 , 1 0 1 , 1 2 1 , 1 2 2 , 1 2 3 , 2 5 6 , 2 5 7 , 2 5 8 , 2 7 8 , 2 7 9 1 1 0 6 0 1 0 2 to 1 2 0 2 5 9 to 2 7 7 1 1 0 4 0 1 2 6 to 2 5 3 4 0 1 1 0 bumped pad height all pad 1 4 ( typ.)
65 com / 96 seg driver & controller for stn lcd S6B0756 4 cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m ( +4128.00 , +1003.00 ) 30 m m 30 m m 30 m m ( +3853.05 , -888.95 ) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-4 278.95 , + 1043.10 ) (+4 316.90 ? 1077.60 ) 42 m m 108 m m when d e signing cog pattern, ito pattern must be prohibited on this area ( ilb align key). if ito pattern is used for routing over this area, it can be happened pattern-short through bumped pattern on ilb align key
S6B0756 65 com / 96 seg driver & controller for stn lcd 5 pad center coordinates table 2 . p ad center coordinates [ u nit: m m] no name x y no name x y no name x y 1 dummy1 -3585.35 -1035 51 vci(vci3) -65.35 -1035 101 dummy6 4243 -577.55 2 dummy2 -3505.35 -1035 52 vci(vci3) 4.65 -1035 102 com31 4243 -497.55 3 test(pad-ck) -3425.35 -1035 53 vci(vci3) 74.65 -1035 103 com30 4243 -437.55 4 test(test_cl) -3355.35 -1035 54 vci(vci3) 144.65 -1035 104 com29 4243 -377.55 5 test3 -3285.35 -1035 55 vci(vci3) 214.65 -1035 105 com28 4243 -317.55 6 test4 -3215.35 -1035 56 vci(vci3) 284.65 -1035 106 com27 4243 -257.55 7 vss -3145.35 -1035 57 vci(vci3) 354.65 -1035 107 com26 4243 -197.55 8 ps0 -3075.35 -1035 58 vss(vss0) 424.65 -1035 108 com25 4243 -137.55 9 vdd1 -3005.35 -1035 59 vss(vss1) 494.65 -1035 109 com24 4243 -77.55 10 ps1 -2935.35 -1035 60 vss(vss1) 564.65 -1035 110 com23 4243 -17.55 11 vss -2865.35 -1035 61 vss(vss1) 634.65 -1035 111 com22 4243 42.45 12 cs1b -2795.35 -1035 62 vss(vss1) 704.65 -1035 112 com21 4243 102.45 13 cs1b -2725.35 -1035 63 vss(vss1) 774.65 -1035 113 com20 4243 162.45 14 vdd1 -2655.35 -1035 64 vss(vss2) 844.65 -1035 114 com19 4243 222.45 15 resetb -2585.35 -1035 65 vss(vss2) 914.65 -1035 115 com18 4243 282.45 16 rs -2515.35 -1035 66 vss(vss2) 984.65 -1035 116 com17 4243 342.45 17 rs -2445.35 -1035 67 vss(vss2) 1054.65 -1035 117 com16 4243 402.45 18 rs -2375.35 -1035 68 vss(vss2) 1124.65 -1035 118 com15 4243 462.45 19 vss -2305.35 -1035 69 vss(vss2) 1194.65 -1035 119 com14 4243 522.45 20 rw_wr -2235.35 -1035 70 vss(vss2) 1264.65 -1035 120 com13 4243 582.45 21 rw_wr -2165.35 -1035 71 vss(vss2) 1334.65 -1035 121 dummy7 4243 662.45 22 e_rd -2095.35 -1035 72 vss(vss2) 1404.65 -1035 122 dummy8 4243 742.45 23 e_rd -2025.35 -1035 73 int(vr) 1474.65 -1035 123 dummy9 4243 822.45 24 vdd1 -1955.35 -1035 74 int(vr) 1544.65 -1035 124 dummy10 3969.9 1003 25 db0 -1885.35 -1035 75 vout 1614.65 -1035 125 dummy11 3889.9 1003 26 db1 -1815.35 -1035 76 vout 1684.65 -1035 126 com12 3809.9 1003 27 db2 -1745.35 -1035 77 vout 1754.65 -1035 127 com11 3749.9 1003 28 db3 -1675.35 -1035 78 vout 1824.65 -1035 128 com10 3689.9 1003 29 db4 -1605.35 -1035 79 vout 1894.65 -1035 129 com9 3629.9 1003 30 db5 -1535.35 -1035 80 vout 1964.65 -1035 130 com8 3569.9 1003 31 db6 -1465.35 -1035 81 vout 2034.65 -1035 131 com7 3509.9 1003 32 db6 -1395.35 -1035 82 vout 2104.65 -1035 132 com6 3449.9 1003 33 db7 -1325.35 -1035 83 v1 2174.65 -1035 133 com5 3389.9 1003 34 db7 -1255.35 -1035 84 v1 2244.65 -1035 134 com4 3329.9 1003 35 vdd(vdd1) -1185.35 -1035 85 v2 2314.65 -1035 135 com3 3269.9 1003 36 vdd(vdd1) -1115.35 -1035 86 v2 2384.65 -1035 136 com2 3209.9 1003 37 vdd(vdd1) -1045.35 -1035 87 v3 2454.65 -1035 137 com1 3149.9 1003 38 vdd(vdd1) -975.35 -1035 88 v3 2524.65 -1035 138 com0 3089.9 1003 39 vdd(vdd2) -905.35 -1035 89 v4 2594.65 -1035 139 coms 3029.9 1003 40 vdd(vdd2) -835.35 -1035 90 v4 2664.65 -1035 140 dummy12 2969.9 1003 41 vdd(vdd2) -765.35 -1035 91 otpg 2734.65 -1035 141 dummy13 2909.9 1003 42 vci(vci1) -695.35 -1035 92 otpg 2804.65 -1035 142 seg0 2849.9 1003 43 vci(vci1) -625.35 -1035 93 otpd 2874.65 -1035 143 seg1 2789.9 1003 44 vci(vci1) -555.35 -1035 94 otpd 2944.65 -1035 144 seg2 2729.9 1003 45 vci(vci1) -485.35 -1035 95 dummy 3014.65 -1035 145 seg3 2669.9 1003 46 vci(vci2) -415.35 -1035 96 dummy 3084.65 -1035 146 seg4 2609.9 1003 47 vci(vci2) -345.35 -1035 97 dummy 3154.65 -1035 147 seg5 2549.9 1003 48 vci(vci2) -275.35 -1035 98 dummy3 3234.65 -1035 148 seg6 2489.9 1003 49 vci(vci2) -205.35 -1035 99 dummy4 3314.65 -1035 149 seg7 2429.9 1003 50 vci(vci3) -135.35 -1035 100 dummy5 4243 -657.55 150 seg8 2369.9 1003
65 com / 96 seg driver & controller for stn lcd S6B0756 6 table 2 . p ad center coordinates (continued) [ u nit: m m] no name x y no name x y no name x y 151 seg9 2309.9 1003 201 seg59 -690.1 1003 251 com43 -3690.1 1003 152 seg10 2249.9 1003 202 seg60 -750.1 1003 252 com44 -3750.1 1003 153 seg11 2189.9 1003 203 seg61 -810.1 1003 253 com45 -3810.1 1003 154 seg12 2129.9 1003 204 seg62 -870.1 1003 254 dummy16 -3890.1 1003 155 seg13 2069.9 1003 205 seg63 -930.1 1003 255 dummy17 -3970.1 1003 156 seg14 2009.9 1003 206 seg64 -990.1 1003 256 dummy18 -4243 822.45 157 seg15 1949.9 1003 207 seg65 -1050.1 1003 257 dummy19 -4243 742.45 158 seg16 1889.9 1003 208 seg66 -1110.1 1003 258 dummy20 -4243 662.45 159 seg17 1829.9 1003 209 seg67 -1170.1 1003 259 com46 -4243 582.45 160 seg18 1769.9 1003 210 seg68 -1230.1 1003 260 com47 -4243 522.45 161 seg19 1709.9 1003 211 seg69 -1290.1 1003 261 com48 -4243 462.45 162 seg20 1649.9 1003 212 seg70 -1350.1 1003 262 com49 -4243 402.45 163 seg21 1589.9 1003 213 seg71 -1410.1 1003 263 com50 -4243 342.45 164 seg22 1529.9 1003 214 seg72 -1470.1 1003 264 com51 -4243 282.45 165 seg23 1469.9 1003 215 seg73 -1530.1 1003 265 com52 -4243 222.45 166 seg24 1409.9 1003 216 seg74 -1590.1 1003 266 com53 -4243 162.45 167 seg25 1349.9 1003 217 seg75 -1650.1 1003 267 com54 -4243 102.45 168 seg26 1289.9 1003 218 seg76 -1710.1 1003 268 com55 -4243 42.45 169 seg27 1229.9 1003 219 seg77 -1770.1 1003 269 com56 -4243 -17.55 170 seg28 1169.9 1003 220 seg78 -1830.1 1003 270 com57 -4243 -77.55 171 seg29 1109.9 1003 221 seg79 -1890.1 1003 271 com58 -4243 -137.55 172 seg30 1049.9 1003 222 seg80 -1950.1 1003 272 com59 -4243 -197.55 173 seg31 989.9 1003 223 seg81 -2010.1 1003 273 com60 -4243 -257.55 174 seg32 929.9 1003 224 seg82 -2070.1 1003 274 com61 -4243 -317.55 175 seg33 869.9 1003 225 seg83 -2130.1 1003 275 com62 -4243 -377.55 176 seg34 809.9 1003 226 seg84 -2190.1 1003 276 com63 -4243 -437.55 177 seg35 749.9 1003 227 seg85 -2250.1 1003 277 coms1 -4243 -497.55 178 seg36 689.9 1003 228 seg86 -2310.1 1003 278 dummy21 -4243 -577.55 179 seg37 629.9 1003 229 seg87 -2370.1 1003 279 dummy22 -4243 -657.55 180 seg38 569.9 1003 230 seg88 -2430.1 1003 181 seg39 509.9 1003 231 seg89 -2490.1 1003 182 seg40 449.9 1003 232 seg90 -2550.1 1003 183 seg41 389.9 1003 233 seg91 -2610.1 1003 184 seg42 329.9 1003 234 seg92 -2670.1 1003 185 seg43 269.9 1003 235 seg93 -2730.1 1003 186 seg44 209.9 1003 236 seg94 -2790.1 1003 187 seg45 149.9 1003 237 seg95 -2850.1 1003 188 seg46 89.9 1003 238 dummy14 -2910.1 1003 189 seg47 29.9 1003 239 dummy15 -2970.1 1003 190 seg48 -30.1 1003 240 com32 -3030.1 1003 191 seg49 -90.1 1003 241 com33 -3090.1 1003 192 seg50 -150.1 1003 242 com34 -3150.1 1003 193 seg51 -210.1 1003 243 com35 -3210.1 1003 194 seg52 -270.1 1003 244 com36 -3270.1 1003 195 seg53 -330.1 1003 245 com37 -3330.1 1003 196 seg54 -390.1 1003 246 com38 -3390.1 1003 197 seg55 -450.1 1003 247 com39 -3450.1 1003 198 seg56 -510.1 1003 248 com40 -3510.1 1003 199 seg57 -570.1 1003 249 com41 -3570.1 1003 200 seg58 -630.1 1003 250 com42 -3630.1 1003
S6B0756 65 com / 96 seg driver & controller for stn lcd 7 pin description power supply table 3 . power supply p ins name i/o description v dd1 vdd2 supply power supply v ss0 vss1 vss2 supply ground note: vss0, vss1 and vss2 must be shorted to external wire. lcd driver suppl y voltages the se voltage s are determined by lcd pixel is imped a nce , and converted by operational amplifier s for application. voltages should have the following relation ship ; vout 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd b ias. lcd bias v1 v2 v3 v4 1/n bias (n-1) / n x v out (n-2) / n x v out ( 2/n ) x v out ( 1/n ) x v out v out v1 v2 v3 v4 i/ o note: n = 4 to 9 lcd driver supply table 4 . lcd driver supply p ins name i/o description vout i/o voltage converter input/output pin connect this pin to v ss through capacitor. vci 1 vc i 2 vci3 i voltage converter input voltage pin and power supply pins for analog block voltages should have the following relationship: vdd vci vout
65 com / 96 seg driver & controller for stn lcd S6B0756 8 system control table 5 . system control p ins name i/o description otpg i gate voltage for otp programming otpd i drain voltage for otp programming test1 to test 4 i test pins don ? t use these pins.
S6B0756 65 com / 96 seg driver & controller for stn lcd 9 microprocessor interface table 6 . microprocessor i nterface p ins name i/o description resetb i reset the input pin when resetb is "l", initialization is executed. parallel/serial data input select input ps 0 interface mode data/ instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs or none sid(db7) write only sclk(db6) ps 0 i *note: when ps is "l", db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either "h" or "l". ps1 i microprocessor interface select input pin - ps0 = ? h ? , ps1 = "h": 6800-series parallel mpu interface - ps0 = ? h ? , ps1 = "l": 8080-series parallel mpu interface - ps0 = ? l ? , ps1 = "h": 4 pin-spi serial mpu interface - ps0 = ? l ? , ps1 = "l": 3 pin-spi serial mpu interface cs1b i chip select input pins data/instruction i/o is enabled only when cs1b is "l" . when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin ps1 mpu type rw_wr description h 6800-series rw read/write control input pin - rw = "h": r ead - rw = "l": w rite l 8080-series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
65 com / 96 seg driver & controller for stn lcd S6B0756 10 table 6 (continued) name i/o description read / write execution control pin ps1 mpu type e_rd description h 6800-series e read/write control input pin - rw = "h": when e is "h", db0 to db7 are in an output status. - rw = "l": the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is "l", db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps 0 = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance.
S6B0756 65 com / 96 seg driver & controller for stn lcd 11 lcd driver outputs table 7 . lcd d river o utputs p ins name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m (internal) normal display reverse display h h vout v2 h l v ss v3 l h v2 vout l l v3 v ss power save mode v ss v ss seg0 to seg95 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (internal) common driver output voltage h h v ss h l vout l h v1 l l v4 power save mode v ss com0 to com 63 o coms (coms1) o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. note: dummy ? these pins should be opened (floated).
65 com / 96 seg driver & controller for stn lcd S6B0756 12 functional description microprocessor interface chip select input there are cs1b for chip selection. the S6B0756 can interface with an mpu only when cs1b is "l" . otherwise rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface S6B0756 has four types of interface with an mpu, which are two serial and two parallel interface. this parallel or serial interface is determined by ps 0 pin as shown in table 8 . table 8 . parallel / serial interface mode ps 0 type cs1b ps1 interface mode h 6800-series mpu mode h parallel cs1b l 8080-series mpu mode h 4 pin-spi mpu mode l serial cs1b l 3 pin-spi mpu mode parallel interface (ps 0 = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by ps1 as shown in table 9 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 10 . table 9 . microprocessor selection for parallel interface ps1 cs1b rs e_rd rw_wr db0 to db7 mpu bus h cs1b rs e rw db0 to db7 6800-series l cs1b rs /rd /wr db0 to db7 8080-series table 10 . parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction) note: when e_rd pin is always pulled high for 6800-series interface, it can be used cs1b for enable signal. in this case, interface data is latched at the rising edge of cs1b and t he type of data transfer is determined by signals at rs, rw_wr as in case of 6800-series mode .
S6B0756 65 com / 96 seg driver & controller for stn lcd 13 cs1b rs rw e db command write data w rite status read data read figure 3 . 6800-series mpu interface protocol (ps= ? h ? , mi= ? h ? ) cs1b rs /wr /rd db command write data w rite status read data read figure 4 . 8080-series mpu interface protocol (ps= ? h ? , mi= ? l ? )
65 com / 96 seg driver & controller for stn lcd S6B0756 14 serial interface (ps 0 = "l") when the S6B0756 is active (cs1b= ? l ? ) , serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. the display data/command indication may be controlled either via software or the register select(rs) pin, based on the setting of ps1. when the rs pin is used (ps1 = ? h ? ), data is display data when rs is high, and command data when rs is low. when rs is not used (ps1 = ? l ? ), the lcd driver will receive command from mpu by default. if messages on the data pin are data rather than command, m p u should send data direction command(111 0 1000) to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are send, the following messages will be data rather than command. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is handled as command data. serial mode ps0 ps1 cs1b rs serial-mode with rs pin l h cs1b used serial-mode with software command l l cs1b not used 4 pin-spi interface (ps 0 = "l" , ps1 = " h ") cs1b sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 5 . 4 pin spi timing (rs is used)
S6B0756 65 com / 96 seg driver & controller for stn lcd 15 3 pin-spi interface (ps 0 = "l" , ps1 = " l ") to write data to the ddram, send data direction command in 3-pin spi mode. data is latched at the rising edge of s clk. and the ddram column address pointer will be increased by one automatically. figure 6 . 3 pin spi timing (rs is not used) this command is used in 3-pin spi mode only. it will be two continuous commands, the first byte control s the data direction and inform s the lcd driver the second byte will be number of data bytes will be write. after these two commands sending out, the following messages will be data. if data is stopped in transmitting, i t i s not valid data. new d ata will be transferred serially with most significant bit first. notes: l in spite of transmission of d ata, if cs1b will be disable, state terminates abnormally. next state is initialized. l ddl register value ? 0 ? ? 1 ? , ? 95 ? ? 96 ? . (decimal value) busy flag the b usy f lag indicates whether the S6B0756 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance. sclk cs1b 765 766 767 ~ ~ ~ ~ 0 0 1 7 8 ~ ~ 15 ~ ~ 23 sid msb data in page lsb ddc no. of data 3 byte (1) 2 byte (2) 96 byte 0 (1) set page and column address. set page address : 1 0 1 1 p3 p2 p1 p0 set column address msb : 0 0 0 1 0 y6 y5 y4 set column address lsb : 0 0 0 0 y3 y2 y1 y0 (2) set ddc(data direction command) and no. of data bytes. set data direction command( for spi mode only): 0 1 1 0 0 0 0 0 set no. of data bytes(ddl) : d7 d6 d5 d4 d3d2d1d0
65 com / 96 seg driver & controller for stn lcd S6B0756 16 data transfer the S6B0756 uses bus holder and internal data bus for d ata t ransfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 7 . and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 8 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 7 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+2) figure 8 . read timing
S6B0756 65 com / 96 seg driver & controller for stn lcd 17 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 65 -row by 96-column addressable array. each pixel can be selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly t hrough db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 9 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com0 - - com1 - - com2 - - com3 - - com4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 d isplay data ram lcd display figure 9 . ram-to-lcd data transfer page address circuit this circuit is for providing a p age a ddress to display data ram shown in figure 11 . it incorporates 4-bit p age a ddress register changed by only the "set page" instruction. page a ddress 8 (db3 is " h " , db2 , db1 and db0 is "l") is a special ram area for the icons and display data db0 is only valid. line address circuit this circuit assigns ddram a l ine a ddress corresponding to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 9 . it incorporates 7-bit l ine a ddress register changed by only the i nitial d isplay l ine instruction and 7-bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the l ine ad dress for transferring the 96- bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not access l ine a ddress of icons.
65 com / 96 seg driver & controller for stn lcd S6B0756 18 column address circuit column address circuit has a 7-bit preset counter that provides column address to the display data ram as shown in figure 11 . when set column address msb / lsb instruction is issued, 7-bit [y6:y0] is updated. and, since this address is increased by 1 each a r ead or w rite d ata instruction, microprocessor can access the display data continuously. and t he c olumn a ddress counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc select instruction. refer to the following figure 10 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 92 seg 93 seg 94 seg 95 column address [y6:y0] 00h 01h 02h 03h ... ... 5c h 5d h 5e h 5f h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 10 . the relationship between the column address and the segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
S6B0756 65 com / 96 seg driver & controller for stn lcd 19 figure 11 . display data ram map (initial l ine a ddress = 00h) page 0 page 2 page 1 page 3 page9 page 8 line address com output page address db3 db0 db1 db2 data seg95 seg94 seg1 seg0 seg93 seg92 seg91 seg90 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh com0 com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com51 com50 com49 com48 com47 com45 com46 com44 com31 com52 com61 com60 com59 com58 com57 com55 com56 com54 com53 com62 com63 coms page 6 page 5 page 7 40h 1/57 duty 1/65 duty initial start line address = 00h 38h 39h 3ah 3bh 3ch 3fh 3eh 3dh com43 com41 com42 com40 00 - - - - - 01 02 03 04 05 5a 5b 5c 5d 5e 5f 00 - - - - - 01 02 03 04 05 5a 5b 5c 5d 5e 5f 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 initial line register = 00h 31h 32h 33h 34h 2ch 2bh 2ah 29h 28h 37h 36h 35h 2dh 2fh 30h 27h
65 com / 96 seg driver & controller for stn lcd S6B0756 20 lcd display circuits oscillator this is completely on-chip o scillator and its frequency is nearly independent of v dd . this o scillator signal is used in display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl (internal) , generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 96-bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line signal changes the m by setting internal instruction. driving waveform and internal timing signal are shown in figure 12 .
S6B0756 65 com / 96 seg driver & controller for stn lcd 21 fr(internal) m(internal) 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 cl(internal) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss seg n figure 12 . 2- f rame ac driving waveform ( d uty r atio = 1/65) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn fr(internal) m(internal) 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 cl(internal) figure 13 . n-line inversion driving waveform (n = 5 , duty ratio = 1/ 65 )
65 com / 96 seg driver & controller for stn lcd S6B0756 22 lcd driver circuit 65 -channel common driver and 96-channel segment driver configure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m (internal) signal. com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg2 seg1 seg0 com2 com0 com1 m v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss figure 14 . segment and common timing
S6B0756 65 com / 96 seg driver & controller for stn lcd 23 partial display on lcd the S6B0756 realizes the p artial d isplay function on lcd with low-duty driving for saving power consumption and showing the various display duty. to show the various display duty on lcd, lcd driving duty and bias are programmable via the instruction. and, built-in power supply circuits are controlled by the instruction for adjustin g the lcd d riving voltages figure 15 . reference example for partial display (display duty = 25) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 16 . partial display (partial display duty = 9 , initial com0 = 0) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23
65 com / 96 seg driver & controller for stn lcd S6B0756 24 -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 17 . moving display (partial display duty = 9 , initial com0 = 8 )
S6B0756 65 com / 96 seg driver & controller for stn lcd 25 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by p ower c ontrol instruction. for details, refers to "instruction description". table 11 shows the referenced combinations in using p ower s upply circuits. table 11 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on * external input open only the voltage follower circuits are used 0 0 1 off off on external input open only the external power supply circuits are used 0 0 0 off off off external input external input * : when only the voltage regulator circuits and voltage follower circuits are used, external vout should be the same voltage to operate lcd panel(vlcd). so, voltage regulator circuit operation doesn ? t cause any effect.
65 com / 96 seg driver & controller for stn lcd S6B0756 26 voltage converter circuits these circuits boost up the electric potential between vci and vss to 2, 3, 4 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ? set dc-dc step-up ? instruction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vss vout vss vci c1 vout = 3 x vci vss vout vss vci c1 vout = 2 x vci figure 18 . two times boosting circuit figure 19 . three times boosting circuit vss vout c1 vss vci vout = 4 x vci figure 20 . four times boosting circuit
S6B0756 65 com / 96 seg driver & controller for stn lcd 27 voltage regulator circuits the function of the internal v oltage r egulator circuits is to determine liquid crystal operating voltage, v out , by adjusting resistors, ra and rb . because vout is the operating voltage of operational-amplifier circuits shown in figure 21 , it is necessary to be applied internally. for the eq. 1, we determine v out by ra, rb and v ev . the ra and rb are connected internally. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta= 25 c is shown in table 12 (abbreviated otp calibration in v ev expression (eq.2), see ? otp calibration mode ? section for more information ) rb v out = (1 + ???? ) x v ev [v] ------ (eq. 1) ra (63 ? ( a ov/2 ) v ev = (1 - ???????? ) x v ref [v] ------ (eq. 2) 210 table 12 . . v ref voltage at ta = 25 c temp. coefficient v ref [ v ] -0.05% / c 2.1 vev (constant voltage source + electronic volume) + ? internal rb internal ra vout gnd dcdc converter figure 21 . internal voltage regulator circuit
65 com / 96 seg driver & controller for stn lcd S6B0756 28 in case of using internal resistors, ra and rb resistor ra is connected internally between vr pin and v ss , and rb is connected between vout and vr. we determine vout by two instructions, "regulator resistor select" and "set reference voltage". table 13 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 2. 3 3. 0 3 . 7 4 . 4 5 . 1 5 . 8 6 . 5 7 . 2 figure 22 shows vout voltage measured by adjusting internal regulator register ratio (rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 0 8 16 24 32 40 48 56 electronic volume register (0 to 63) v0 voltage [v] (1, 1, 1) 63 63 (1, 1, 0) (1, 0, 1) (1, 0 ,0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) figure 22 . electronic volume level (temp. coefficient = -0.05% / c)
S6B0756 65 com / 96 seg driver & controller for stn lcd 29 voltage follower circuits vlcd voltage (vout) is resistively divided into four voltage levels (v1, v2, v3 and v4), and those output impedance are converted by the v oltage f ollower for increasing drive capability. table 14 shows the relationship between v1 to v4 level and each duty ratio. table 14 lcd bias v1 v2 v3 v4 remarks 1/n (n-1)/n x vout (n- 2 )/n x vout 2/n x vout 1/n x vout n = 4 to 9
65 com / 96 seg driver & controller for stn lcd S6B0756 30 reference circuit examples [ c1 = 1.0 to 4.7 [ m f ] ] figure 23 . when using a ll lcd power circuits (v/c: o n , v/r: o n , v/f: o n ) figure 24 . when using o nly voltage follower circuit (v/c: o ff , v/r: on, v/f: o n ) using internal regulator resistors vout v1 v2 v3 v4 vss vss1 vss2 c1 - + vout v1 v2 v3 v4 external power supply vss vss1 vss2
S6B0756 65 com / 96 seg driver & controller for stn lcd 31 figure 25 . when using o nly voltage follower circuit (v/c: o ff , v/r: o ff , v/f: o n ) figure 26 . when not using a ll lcd power circuits (v/c: o ff , v/r: o ff , v/f: o ff ) vout v1 v2 v3 v4 external power supply vss vss1 vss2 vss vout v1 v2 v3 v4 vss1 vss2 external power supply
65 com / 96 seg driver & controller for stn lcd S6B0756 32 reset circuit setting resetb to " l " or reset instruction can initialize internal function. when resetb becomes " l " , following procedure is occurred. page address : 0 column address: 0 modify-read: off display on / off: off initial display line: 0 (first) initial com0 register: 0 (com0) partial display duty ratio: 1/ 64 icon enable/disable : 0 (disable) reverse display on / off: off (normal) n-line inversion register: 0 (disable) entire display on / off: off (normal) otp_mode on/off : on (normal) power control register (vc, vr, vf) = (0, 0, 0 ) dc-dc step up: 2 times converter circuit = (1, 1) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register: (ev5, ev4, ev3, ev2, ev1, evout) = (1, 0, 0, 0, 0, 0) offset voltage control register ( o v4, o v3, o v2, o v1, o vout) = (0, 0, 0, 0, 0) lcd bias ratio: 1/ 9 shl select: off (normal) adc select: off (normal) oscillator status: off power save mode: release frame frequency : 75hz when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 modify-read: off initial display line: 0 (first) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register (ev5, ev4, ev3, ev2, ev1, evout) = (1, 0, 0, 0, 0, 0) other instruction registers : not changed while resetb is " l " or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db5. after db5 becomes " l " , any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before use.
S6B0756 65 com / 96 seg driver & controller for stn lcd 33 instruction description table 15 . instruction table : don ? t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy on res oprt 0 0 0 0 read the internal status set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 0 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode display on / off 0 0 1 0 1 0 1 1 1 d d = 0: display off d = 1: display on 0 0 0 1 0 0 0 0 set initial display line register 0 0 s6 s5 s4 s3 s2 s1 s0 2-byte i nstruction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set initial com0 register 0 0 c5 c4 c3 c2 c1 c0 2-byte i nstruction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set partial display duty ratio 0 0 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to set partial display duty ratio frame frequency 0 0 1 1 0 1 1 f2 f1 f0 programmable frame frequency 0 0 0 1 0 0 1 1 set n-line inversion 0 0 n4 n3 n2 n 1 n0 2-byte i nstruction to set n-line inversion register release n-line inversion 0 0 1 1 1 0 0 1 0 0 release n-line inversion mode reverse display on / off 0 0 1 0 1 0 0 1 1 rev rev = 0: normal display rev = 1: reverse display icon enable/disable 0 0 1 0 1 0 0 0 1 i i = 0 : icon disable i = 1 : icon enable entire display on / off 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on
65 com / 96 seg driver & controller for stn lcd S6B0756 34 table 1 7 . instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc-dc step-up 0 0 0 1 1 0 0 1 dc1 dc0 select the step-up of the internal voltage converter select regulator resistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 x x ev5 ev4 ev3 ev2 ev1 ev 0 2-byte i nstruction to specify the electronic volume register 0 0 1 1 1 0 1 0 1 0 set offset volume register 0 0 x x x o v 4 o v 3 o v 2 o v 1 o v 0 2-byte i nstruction to specify the offset volume register select lcd bias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias otp_mode on 0 0 1 1 1 0 1 1 0 oton otp_mode on/off otp write enable 0 0 1 1 1 0 1 1 1 1 otp write enable shl select 0 0 1 1 0 0 shl com bi-directional selection shl = 0: normal direction shl = 1: reverse direction adc select 0 0 1 0 1 0 0 0 0 adc seg bi-directional selection adc = 0: normal direction adc = 1: reverse direction 1 1 1 0 1 0 0 0 set data direction & display data length(ddl) d7 d6 d5 d4 d3 d2 d1 d0 2-byte instruction to specify the number of data bytes(spi mode) . oscillator on start 0 0 1 0 1 0 1 0 1 1 start the built-in oscillator set power save mode 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
S6B0756 65 com / 96 seg driver & controller for stn lcd 35 read display data 8-bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display d ata cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8-bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incremented by 1 automatically so that the microprocessor can sequential ly w rite data to the addressed page. during auto-increment, the column address wraps to 0 after the last column is written . rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data d ata w rite s et co lumn a ddress s et p age address o ptional s tatus c olumn = co lumn +1 n o y es data w rite c ontinue ? d ummy d ata r ead s et c olumn a ddress s et p age a ddress o ptional s tatus c olumn = c olumn +1 n o y es d ata r ead c ontinue ? d ata r ead c olumn = c olumn +1 figure 27 . sequence for writing display data figure 28 . sequence for reading display data
65 com / 96 seg driver & controller for stn lcd S6B0756 36 read status indicates the internal status of the S6B0756 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy on res oprt 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy. on indicates display on / off status. 0: display on, 1: display off res indicates the initialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset. oprt indicates otp s tatus. 0: otp is programmable , 1: otp is programmed. set page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age ad dress and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 selected page description 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : 0 1 1 1 7 accessible pages for displaying dot-matrix display data 1 0 0 0 8 accessible page for displaying icons : : : : : 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 not accessible page. do not use these pages.
S6B0756 65 com / 96 seg driver & controller for stn lcd 37 set column address sets the c olumn a ddress of display ram from the microprocessor into the column address register. along with the page a ddress, the column address defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, c olumn a ddresses are automatically incremented. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 selected column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 : : : : : : : : : : : : : : : : : : : : : : : : 1 0 1 1 1 0 1 93 1 0 1 1 1 1 0 94 1 0 1 1 1 1 1 95 1 1 x x x x x not used
65 com / 96 seg driver & controller for stn lcd S6B0756 38 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify-read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify-read this instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify -r ead instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess n o y es change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 29 . sequence for cursor display
S6B0756 65 com / 96 seg driver & controller for stn lcd 39 display on / off turns the display on or off . this command has priority over entire display on/off and reverse display on/off. commands are accepted while the display is off, but the visual state of the display does not change. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d d = 1: display on d = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2-byte instruction. the ram display data is displayed at the top row (com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s6 s5 s4 s3 s2 s1 s0 s6 s5 s4 s3 s2 s1 s0 selected line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 0 1 1 1 1 1 0 62 0 1 1 1 1 1 1 63 1 0 0 0 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i initial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 30 . the sequence for setting the initial display line
65 com / 96 seg driver & controller for stn lcd S6B0756 40 set initial com0 register sets the initial row (com 0 ) of the lcd panel using the 2-byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c5 c4 c3 c2 c1 c0 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 com0 0 0 0 0 0 1 com1 0 0 0 0 1 0 com2 0 0 0 0 1 1 com3 : : : : : : : 1 1 1 1 0 0 com 60 1 1 1 1 0 1 com 61 1 1 1 1 1 0 com 62 1 1 1 1 1 1 com 63 2 nd i nstruction ( i nitial com0 s etting) setting i nitial com0 e nd end 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 31 . sequence for setting the initial com0
S6B0756 65 com / 96 seg driver & controller for stn lcd 41 set partial display duty ratio when the icon mode is disable, sets the duty ratio within range of 16 to 64 to realize partial display by using the 2-byte instruction. when the icon mode is enable, sets the duty ratio within range of 17 to 65 to realize partial display by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d6 d5 d4 d3 d2 d1 d0 icon enable/disable bit = 0 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 0 0 0 0 : : : : : : : 0 0 1 0 0 0 0 no operation 0 0 1 0 0 0 0 1/ 16 0 0 1 0 0 0 1 1/1 7 0 0 1 0 0 1 0 1/1 8 0 0 1 0 0 1 1 1/1 9 : : : : : : : : 0 1 1 1 1 0 1 1/ 61 0 1 1 1 1 1 0 1/ 62 0 1 1 1 1 1 1 1/ 63 1 0 0 0 0 0 0 1/ 64 1 0 0 0 0 1 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 32 . sequence for setting partial display
65 com / 96 seg driver & controller for stn lcd S6B0756 42 icon enable/disable bit = 1 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 0 0 0 0 : : : : : : : 0 0 1 0 0 0 0 no operation 0 0 1 0 0 0 1 1/1 7 0 0 1 0 0 1 0 1/1 8 0 0 1 0 0 1 1 1/1 9 0 0 1 0 1 0 0 1/20 : : : : : : : : 0 1 1 1 1 1 0 1/ 62 0 1 1 1 1 1 1 1/ 63 1 0 0 0 0 0 0 1/64 1 0 0 0 0 0 1 1/65 1 0 0 0 0 1 0 : : : : : : : 1 1 1 1 1 1 1 no operation figure 33 . display example when icon is on or off note : once coms is used, icon can be turned off only by using memory data. com0 com63 coms com62 com1 com0 com63 coms com62 com1 com0 com63 coms com62 com1 com0 com63 coms com62 com1 partial duty ratio = 1/64 icon on icon on icon off icon off partial duty ratio = 1/65 not available
S6B0756 65 com / 96 seg driver & controller for stn lcd 43 programmable frame frequency sets the frame frequency to compensate lcd flicking rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 1 1 f2 f1 f0 f2 f1 f0 frame frequency 0 0 0 69hz 0 0 1 73hz 0 1 0 75hz(default value) 0 1 1 81hz 1 0 0 85hz 1 0 1 89hz 1 1 0 93hz 1 1 1 97hz
65 com / 96 seg driver & controller for stn lcd S6B0756 44 set n-line inversion register sets the inverted line number within range of 3 to 3 3 to improve the display quality by controlling the phase of the internal lcd ac signal ( internal m) by using the 2-byte instruction. the dc-bias problem could be occurred if k is even number. so, we recommend customers to set k to be odd number. k : d/n d : the number of display duty ratio (d is selectable by customers) n : n for n-line inversion (n is selectable by customers). the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n-line inversion 0 0 0 0 0 0-line inversion (frame inversion) 0 0 0 0 1 3-line inversion 0 0 0 1 0 4-line inversion : : : : : : 1 1 1 0 1 31-line inversion 1 1 1 1 0 32-line inversion 1 1 1 1 1 33-line inversion 2 nd i nstruction ( n -line i nversion s etting) setting n -line i nversion e nd 1 st i nstruction ( m ode s etting) setting n -line i nversion s tart figure 34 . sequence for setting partial display release n-line inversion returns to the frame inversion condition from the n-line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0
S6B0756 65 com / 96 seg driver & controller for stn lcd 45 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated icon enable / disable allows the icon driver circuit to be enabled or disabled, thus changing the duty ratio setting. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 i i duty range 0 (disable) 1/16 ~ 1/64 1 (enable) 1/17 ~ 1/65 entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the r everse d isplay on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (entire) lcd pixel is illuminated lcd pixel is illuminated otp_mode on/off allows module maker to be able to calibrate. because initial value is on, mode is changed to off for calibration. in otp_mode_off, offset volume is changable. after calibration, calibration offset volume is stored as otp offset volume by otp write enable. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 0 omon omon = 1 : otp_mode on omon = 0 : otp_mode off
65 com / 96 seg driver & controller for stn lcd S6B0756 46 otp write enable allow otp offset volume, which is determined as suitable value, to be programmed on otp cell. once programmed, an otp cell can not be reprogrammed. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 1 power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on select dc-dc step-up selects one of 4 dc-dc step-up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc-dc converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 not used 1 1 2 times boosting circuit
S6B0756 65 com / 96 seg driver & controller for stn lcd 47 regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to table 13. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb / ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
65 com / 96 seg driver & controller for stn lcd S6B0756 48 set electronic volume register consists of 2-byte instruction the 1 st instruction sets electronic volume mode, the 2 nd one updates the contents of electronic volume register. after second instruction, electronic volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 ev5 ev4 ev3 ev2 ev1 ev 0 ev5 ev4 ev3 ev2 ev1 evout reference voltage ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd i nstruction for r egister s etting setting e lectronic v olume e nd 1 st i nstruction for m ode s etting setting e lectronic v olume s tart figure 35 . sequence for setting the electronic volume
S6B0756 65 com / 96 seg driver & controller for stn lcd 49 set offset volume register consists of 2-byte instruction the 1 st instruction sets offset volume mode, the 2 nd one updates the contents of offset volume register. after second instruction, offset volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 x o v4 o v3 o v2 o v1 o v 0 ev4 ev3 ev2 ev1 evout reference voltage ( x ) 0 1 1 1 1 15 0 1 1 1 0 14 : : : : : : : : : : : : 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 -1 1 1 1 1 0 -2 1 1 1 0 1 -3 : : : : : : : : : : : : 1 0 0 0 1 -15 1 0 0 0 0 -16 2 nd i nstruction for r egister s etting setting offset v olume e nd 1 st i nstruction for m ode s etting setting offset v olume s tart figure 36 . sequence for setting the offset volume
65 com / 96 seg driver & controller for stn lcd S6B0756 50 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 selected lcd bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 0 1/ 9 1 1 1 1/ 9 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl = 0: normal direction (com0 ? com 63 ) shl = 1: reverse direction (com 63 ? com0) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins c ould be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg0 ? seg95) adc = 1: reverse direction (seg95 ? seg0)
S6B0756 65 com / 96 seg driver & controller for stn lcd 51 set data direction & display data length (3-pin spi mode) consists of two bytes instruction. this command is used in 3-pin spi mode only (ps0 = ? l ? and ps1 = ? l ? ) . it will be two continuous commands, the first byte control the data direction (write mode only) and inform the lcd driver the second byte will be number of data bytes will be write. when rs is not used, the display data length instruction is used to indicate that a specified number of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 1 1 0 1 0 0 0 the 2 nd instruction: set display data length (ddl) register rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d 0 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 oscillator on start this instruction enables the built-in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 reset this instruction r esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply, which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
65 com / 96 seg driver & controller for stn lcd S6B0756 52 power save the S6B0756 enters the power save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 release sleep mode sleep mode (p=1) oscillator circuits: off lcd power supply circuits: off all com / seg output level: vss set power save mode release power save mode figure 37 . power save routine n op no operation instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 test instruction this instruction is for test only. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1
S6B0756 65 com / 96 seg driver & controller for stn lcd 53 referential instruction setup flow: initializing with the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power resetb pin = "h" user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of initialization figure 38 . initializing w ith the built- i n power supply circuits
65 com / 96 seg driver & controller for stn lcd S6B0756 54 referential instruction setup flow: initializing without the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save figure 39 . initializing w ithout the built- i n power supply circuits
S6B0756 65 com / 96 seg driver & controller for stn lcd 55 referential instruction setup flow: data displaying end of initialization write display data by instruction [display data write] turn display on / off instruction [display on / off] end of data display display data ram addressing by instruction [initial display line] [set page address] [set column address] figure 40 . data displaying r eferential instruction setup flow: power off optional status power off (vdd-vss) end of power off set power save by instruction figure 41 . power o ff
65 com / 96 seg driver & controller for stn lcd S6B0756 56 referential instruction setup flow: partial duty changing start of partial changing set display off by internal instruction [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set standby mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels figure 42 . partial duty changing note :1. partial com0 r egister s etting for com h/w half: [64 ? ( u ser d uty) ] / 2
S6B0756 65 com / 96 seg driver & controller for stn lcd 57 specifications absolute maximum ratings table 16 . absolute maximum ratings (v ss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 4.0 v v out - 0.3 ~ + 13 . 5 v supply voltage range v 1 , v 2 , v 3 , v 4 - 0.3 ~ vout + 0.3 v input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 20 ~ + 70 c storage temperature range t str - 20 ~ + 70 c notes: 1. vdd, vout, v1 to v4, vext and vci are based on v ss = 0v. 2. voltage vout 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
65 com / 96 seg driver & controller for stn lcd S6B0756 58 dc characteristics table 17 . dc characteristics (v ss = 0v, v dd = 1 . 8 ~ 3 . 3 v, ta=-20~70 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 1 . 8 - 3 . 3 v v dd *1 operating voltage (2) vout 4.0 - 12 .0 v vout, *2 high v ih 0. 8 v dd - v dd input voltage low v il v ss - 0. 2 v dd v *3 high v oh i oh = -0.5ma 0. 8 v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0. 2 v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a *3 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a *5 lcd driver on resistance r on ta = 25 c, vout = 8v - 2.0 3.0 k w segn comn *6 frame frequency f fr ta = 25 c 65 75 100 hz *7 table 18 . dc characteristics item symbol condition min. typ. max. unit pin used voltage converter circuit output voltage v out 2 / 3 / 4 voltage conversion (no-load ) 95 99 - % vout voltage regulator circuit operating voltage v out 4.0 - 12.0 v vout voltage follower circuit operating voltage v out 4.0 - 12 .0 v vout * 8 reference voltage v ref ta = 25 c 2.04 2. 10 2. 1 6 v * 9
S6B0756 65 com / 96 seg driver & controller for stn lcd 59 dynamic current consumption (1) when an external power supply is used. table 19 . dynamic current 1 (external power) (v dd = 2.4 v, ta = 25 c) item symbol condition min typ max unit pin used v out -v ss =9.0v , duty = 1/ 65 no load (display off) - - 20 m a *10 dynamic current consumption (1) i dd1 v out -v ss = 9 .0v, duty = 1/ 65 no load (display on , checker pattern) - - 20 m a *10 dynamic current consumption (2) when the internal power supply is on table 20 . . dynamic current 2 (internal power) (v dd = 2.4 v, ta = 25 c) item symbol condition min. typ. max. unit pin used vci=2.75v, x 4 boosting, duty = 1/ 65 , ev=32, rr=3, no load (display off) - 100 150 m a *10 dynamic current consumption (2) i dd2 vci=2.75v, x 4 boosting, duty = 1/ 65 , ev=32, rr=3 no load (display on , checker pattern) - 100 150 m a * 10 current consumption during power save mode table 21 . power save mode current (v dd = 2.4 v, ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during sleep - 2 9 m a *10
65 com / 96 seg driver & controller for stn lcd S6B0756 60 table 22 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on-chip oscillator circuit is used f fr x n f fr x 4 x n (f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 17 to 65 ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, rs, db0 to db7, e_rd, rw_wr, resetb, ps1 , ps 0 *4 . db0 to db7 *5 . applies when the db0 to db7 pins are in high impedance. *6 . resistance value when -0.1[ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ma] ( d v : voltage change when -0.1[ma] is applied in the on status.) *7 . see table 22 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v out within the voltage follower operating voltage range. *9 . on-chip reference voltage source of the voltage regulator circuit to adjust v out . *10 . applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors(rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
S6B0756 65 com / 96 seg driver & controller for stn lcd 61 ac characteristics read / write characteristics (8080-series mp) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwlw , t pwlr t cy80 t ah80 t as80 db0 to db7 ( write ) db0 to db7 ( read ) /rd, /wr cs1b rs t pwhw , t pwhr figure 43 . read / write characteristics ( 8080-series mpu) table 23 (v dd = 1.8 ~ 3 . 3 v, ta = -20 ~ +70 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time t cy80 500 - ns pulse width low for write pulse width high for write rw_wr (/wr) t pwlw t pwhw 12 0 12 0 - - ns pulse width low for read pulse width high for read e_rd (/rd) t pwlr t pwhr 24 0 12 0 - - ns data setup time data hold time t ds80 t dh80 8 0 30 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf - 10 28 0 2 00 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t cy80 - t pwlw - t pwhw ) for write, (tr + tf) < (t cy80 - t pwlr - t pwhr ) for read
65 com / 96 seg driver & controller for stn lcd S6B0756 62 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewhw , t ewhr t cy68 t ah68 t as68 db0 to db7 ( write ) db0 to db7 ( read ) e cs1b rs, r/w t ewlw , t ewlr figure 44 . read / write characteristics (6800-series microprocessor) table 24 (v dd = 1.8 ~ 3.3 v, ta = -20 ~ +70 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time t cy68 500 - ns enable width high for write enable width low for write e_rd (e) t ewhw t ewlw 12 0 12 0 - - ns enable width high for read enable width low for read e_rd (e) t ewhr t ewlr 24 0 12 0 - - ns data setup time data hold time t ds68 t dh68 30 5 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf - 10 6 0 5 0 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy68 - tewhw - tewlw ) for write, (tr + tf) < (tcy68 - tewhr - tewlr ) for read
S6B0756 65 com / 96 seg driver & controller for stn lcd 63 serial interface characteristics db7 ( sid ) db6 ( sclk ) rs cs1b t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 45 table 25 (v dd = 1 . 8 v, ta = -20 ~ +70 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) ts cy ts hw ts lw 1 11 60 60 - - - ns address setup time address hold time rs t ass t ahs 6 0 6 0 - - ns data setup time data hold time db7 (sid) t dss t dhs 6 0 6 0 - - ns cs1b setup time cs1b hold time cs1b t css t chs 6 0 6 0 - - ns (v dd = 2.7v , ta = -20 ~ +70 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) ts cy ts hw ts lw 58.8 30 30 - - ns address setup time address hold time rs t ass t ahs 3 0 3 0 - - ns data setup time data hold time db7 (sid) t dss t dhs 3 0 3 0 - - ns cs1b setup time cs1b hold time cs1b t css t chs 3 0 3 0 - - ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
65 com / 96 seg driver & controller for stn lcd S6B0756 64 reset input timing resetb internal status t rw t r reset complete during reset figure 46 table 26 (v dd = 1 . 8 ~ 3.3 v, ta = -20 ~ +70 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 1000 - ns reset time - t r - 1000 ns
S6B0756 65 com / 96 seg driver & controller for stn lcd 65 reference applications microprocessor interface in case of interfacing with 6800-series (ps 0 = " h ", ps1 = "h") 6800-series mpu cs1b rs e_rd rw_wr db0 to db7 resetb ps0 ps1 S6B0756 db0 to db7 resetb v dd v dd rw e rs cs1b figure 47 . interfacing with 6800-series in case of interfacing with 8080-series (ps 0 = " h " , ps1 = "l" ) 80 8 0-series mpu cs1b rs e_rd rw_wr db0 to db7 resetb ps0 ps1 S6B0756 db0 to db7 resetb v ss v dd wr /rd rs cs1b figure 48 . interfacing with 8080-series
65 com / 96 seg driver & controller for stn lcd S6B0756 66 in case of serial peripheral interface with rs pin (ps0 = "l" , ps1 = " h " ) mpu ps0 ps1 S6B0756 v dd v ss db0 to db5 open cs1b cs1b rs rs resetb resetb db6(sclk) sclk db7(sid) sid figure 49 . serial interface in case of serial peripheral interface with software command (ps0 = "l" , ps1 = "l" ) mpu ps0 ps1 S6B0756 v ss v ss db0 to db5 open cs1b cs1b rs vss/vdd resetb resetb db6(sclk) sclk db7(sid) sid figure 50 . serial interface
S6B0756 65 com / 96 seg driver & controller for stn lcd 67 connections between S6B0756 and lcd panel single chip configurations (1/ 65 duty) com 31 : com 0 coms coms1 com 63 : com 32 seg 95 ........... seg 0 s 6b 07 56 ( bottom view) com 31 : com 0 coms coms1 com 63 : com 32 seg 0 ......... seg 95 s 6b 07 56 ( top view) ? a x a ? a x a 64 96 pixels ? a x a ? a x a 64 96 pixels figure 51 . shl = 0, adc = 1 figure 52 . shl = 0, adc = 0 ? a x a ? a x a coms com 0 : co m31 co m32 : com 63 coms1 se g95 ........... se g0 s 6b 07 56 ( top view) ? a x a ? a x a 64 96 pixels com 32 : com 63 coms1 coms com 0 : com 31 seg 0 .......... seg 95 s 6b 07 56 ( bottom view) 64 96 pixels figure 53 . shl = 1, adc = 0 figure 54 . shl = 1, adc = 1
65 com / 96 seg driver & controller for stn lcd S6B0756 68 otp calibration mode sequence for setting the modified electronic volume - next figure is a block diagram of sequence for setting the modified electronic volume. otp calibration 5bit offset (otp_ov) inst calibration 5bit offset (inst_ov) mux electronic volume 6bit level (ev) adder 0 1 otp_mode on/off modified ev 7bit level (mev) otp writing process figure 55 . s equence for setting the modified electronic volume initially, otp cell is not programmed and has 5'b00000 value. when the external reset is applied, otp_mode is on. mev is ev + otp_ov. since otp_ov is 5'b00000, mev is ev. for vout calibration the instruction "otp_mode_off" is executed, and then mev is ev + ov and user can adjust mev value using the instruction "set offset volume register". when mev overflows or underflows, mev will be saturated. repeat this step until end of the calibration. if vout calibration is suitable, otp_writing process is executed, and then otp cell is programmed and otp_ov is programmed with ov. finally, vout calibration process is finished. again, when the external reset is applied, otp_mode is on. mev is ev + otp_ov. accordingly mev is the ev which has always the offset with otp_ov value. but if programmed otp_ov is unlike, the instruction "otp_mode off" can be executed and then mev will be ev + ov. accordingly ov can be adjusted with instructions although otp cell is programmed.
S6B0756 65 com / 96 seg driver & controller for stn lcd 69 eprom cell structure otp(one time programmable) has been implemented on the S6B0756. the eprom stores the offset volume for vout calibration after the device has been assembled and calibrated on a lcd module. for otp programming, otpd pin and otpg pin are used. those pins should be made available on the module glass the otp block of the S6B0756 consists of 6 bits. 1 bit is used for otp mode protection bit(oprt), and 5 bits are used for vout calibration(ov4~ov0). eprom block msb lsb oprt ov4 ov3 ov2 ov1 ov0 description -. oprt : the offset volume(ov) can be written to eprom only when oprt bit = ? 0 ? ov4~ov0 : the ov is used for calibrating the vout voltage as an offset to the ev register value. vout calibration flow vout may be calibrated with otp in the following order.(ex : ex = 32, ov=-3) step rs rw db7 db6 db5 db4 db3 db2 db1 db0 description 1. apply external reset 0 0 1 0 0 0 0 0 0 1 2 0 0 x x 1 0 0 0 0 0 set electronic volume by using instruction(ev = 32) 3 0 0 1 1 1 0 1 1 0 0 otp_mode_off by using the instruction 0 0 1 1 1 0 1 0 1 0 4. 0 0 x x x 1 1 1 0 1 set offset volume by using the instruction(ov = -3) 5. repeat step 4. until the end of the calibration 6. 0 0 1 0 1 0 1 0 0 1 set power save mode(p=1) 7. 0 0 1 1 1 0 1 1 1 1 otp write enable ( only when oprt = 0 ) 8. apply programming voltages for otp programming (otpg, otpd) 9. cut off programming voltages for otp programming(otpg,otpd) 10. apply external reset
65 com / 96 seg driver & controller for stn lcd S6B0756 70 after the external reset, the calibrated data are automatically transferred to the 5-bit reference voltage control register. *step 6,7,8,9,10 is otp_writing process. *otp_writing process is available when oprt is zero (if oprt = 1, otp cell is not programmed). voltages and waveforms for otp programming power save on otp write enable otpg otpd resetb 10v* 12.5v * otp write mode t1 t2 t3 t4 t5 figure 56 . voltages and waveforms for otp programming( otp_writing process) * note : voltages for otpg and otpd may be changed. specific timings(t1~t5) timing min max t1,t2, t4, t5 100us - t3 100ms -

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